Accurate computation of field reject ratio based on fault latency

The field reject ratio, the fraction of defective devices that pass the acceptance test, is a measure of the quality of the tested product. Although the assessment of quality is important, a n accurate measurement of the field reject ratio of tested VLSI chips is often not feasible. We show that the known methods of field reject ratio prediction a re not accurate since they fail to realistically model the process of testing. We model the detection of a fault by a n input test vector as a random event. However, we recognize that the detection of a fault may be delayed for various reasons: the fault may be detectable only by application of a sequence of vectors or it may not have been targeted until later. In our statistical model, a fault is characterized by two parameters: a per-vector detection probability and an integer-valued latency. Irrespective of the detection probability, the fault cannot be detected by a vector sequence shorter than its latency. The circuit is characterized by the joint distribution of latency and detection probability over all faults. This distribution, obtained by applying the Bayes’ rule to the actual test data, enables us to compute the field reject ratio. The sensitivity of this approach to variations in the measured parameters is also investigated.